clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider
authorDmitry Osipenko <digetx@gmail.com>
Thu, 11 Apr 2019 21:48:34 +0000 (00:48 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sat, 25 May 2019 16:25:20 +0000 (18:25 +0200)
commit2b49eeb37896216a762b61b13f09a182e04504a6
treebd66f414a8ee64094f91d2e556b227bdb77c21fd
parent70cd1fdad2e99e8e10373c54dd9bb81957233a27
clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider

commit 40db569d6769ffa3864fd1b89616b1a7323568a8 upstream.

There are wrongly set parenthesis in the code that are resulting in a
wrong configuration being programmed for PLLM. The original fix was made
by Danny Huang in the downstream kernel. The patch was tested on Nyan Big
Tegra124 chromebook, PLLM rate changing works correctly now and system
doesn't lock up after changing the PLLM rate due to EMC scaling.

Cc: <stable@vger.kernel.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/clk/tegra/clk-pll.c