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(parent: 35807de) | patch
clk: qcom: msm8960: fix ce3_core clk enable register
authorSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Mon, 22 Feb 2016 11:43:39 +0000 (11:43 +0000)
committerSasha Levin <sasha.levin@oracle.com>
Tue, 12 Jul 2016 12:48:01 +0000 (08:48 -0400)
commit66e0e452e09345e95d7fa781d6d3c0c36c47b438
tree3dcf7216531ace00bf130a6f337ac2ccc04aea32tree | snapshot
parent35807de76e1c2b7d15eea2f947983fcd043a2db0commit | diff
clk: qcom: msm8960: fix ce3_core clk enable register

[ Upstream commit 732d6913691848db9fabaa6a25b4d6fad10ddccf ]

This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
drivers/clk/qcom/gcc-msm8960.c diff | blob | history
wrapfs-4.14.y