drm/i915/gvt: Set SNOOP for PAT3 on BXT/APL to workaround GPU BB hang
authorColin Xu <colin.xu@intel.com>
Wed, 17 Mar 2021 02:55:00 +0000 (10:55 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sat, 20 Mar 2021 09:39:46 +0000 (10:39 +0100)
commit8cd68991b836feb73dccf72a9ffa222ba4c6dab4
tree88c3d59552b5a4ff035b4d27dde382458cb3861b
parent50f83ffc58ab6f23332a1ba18f687f285db16bcc
drm/i915/gvt: Set SNOOP for PAT3 on BXT/APL to workaround GPU BB hang

commit 8fe105679765700378eb328495fcfe1566cdbbd0 upstream

If guest fills non-priv bb on ApolloLake/Broxton as Mesa i965 does in:
717e7539124d (i965: Use a WC map and memcpy for the batch instead of pw-)
Due to the missing flush of bb filled by VM vCPU, host GPU hangs on
executing these MI_BATCH_BUFFER.

Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT
PML4 PTE: PAT(0) PCD(1) PWT(1).

The performance is still expected to be low, will need further improvement.

Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Colin Xu <colin.xu@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20201012045231.226748-1-colin.xu@intel.com
(cherry picked from commit 8fe105679765700378eb328495fcfe1566cdbbd0)
Signed-off-by: Colin Xu <colin.xu@intel.com>
Cc: <stable@vger.kernel.org> # 5.4.y
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/gpu/drm/i915/gvt/handlers.c