clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188
authorRomain Perier <romain.perier@gmail.com>
Sun, 23 Aug 2015 09:32:37 +0000 (11:32 +0200)
committerSasha Levin <sasha.levin@oracle.com>
Mon, 18 Apr 2016 12:50:33 +0000 (08:50 -0400)
commita0723dc0436813a4bb543a823b146045eb97f35b
tree003f7ef5473c7cb0a4da0beee7a196fa37345c6a
parent754d2b7064ccfe6ca116323553f3f44d6f6f9d96
clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188

[ Upstream commit 3bba75a2ec32bd5fa7024a4de3b8cf9ee113a76a ]

Now that the rockchip clock subsystem does clock gating with GPIO banks,
these are no longer enabled once during probe and no longer stay enabled
for eternity. When all these clocks are disabled, the parent clock pclk_peri
might be disabled too, as no other child claims it. So, we need to add pclk_peri
to the critical clocks.

Signed-off-by: Romain Perier <romain.perier@gmail.com>
Tested-by: Michael Niewoehner <linux@mniewoehner.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
drivers/clk/rockchip/clk-rk3188.c