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(parent: 864aede) | patch
clk: mvebu: use correct bit for 98DX3236 NAND
authorChris Packham <chris.packham@alliedtelesis.co.nz>
Thu, 24 May 2018 05:23:41 +0000 (17:23 +1200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 21 Nov 2018 08:24:07 +0000 (09:24 +0100)
commitd2aaeb9a8e05442129694d8f206685f01644ba75
tree1e0d7317ec3c4df88d42d93c879f7ce01d1f66cctree | snapshot
parent864aede99f55cfad8be37ae24a02bd92bc5606adcommit | diff
clk: mvebu: use correct bit for 98DX3236 NAND

commit 00c5a926af12a9f0236928dab3dc9faf621406a1 upstream.

The correct fieldbit value for the NAND PLL reload trigger is 27.

Fixes: commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC")
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/clk/mvebu/clk-corediv.c diff | blob | history
wrapfs-5.3.y