ARM: dts/imx6q-bx50v3: Set display interface clock parents

[ Upstream commit 665e7c73a7724a393b4ec92d1ae1e029925ef2b7 ]

Avoid LDB and IPU DI clocks both using the same parent. LDB requires
pasthrough clock to avoid breaking timing while IPU DI does not.

Force IPU DI clocks to use IMX6QDL_CLK_PLL2_PFD0_352M as parent
and LDB to use IMX6QDL_CLK_PLL5_VIDEO_DIV.

This fixes an issue where attempting atomic modeset while using
HDMI and display port at the same time causes LDB clock programming
to destroy the programming of HDMI that was done during the same
modeset.

Cc: stable@vger.kernel.org
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
[Use IMX6QDL_CLK_PLL2_PFD0_352M instead of IMX6QDL_CLK_PLL2_PFD2_396M
 originally chosen by Robert Beckett to avoid affecting eMMC clock
 by DRM atomic updates]
Signed-off-by: Ian Ray <ian.ray@ge.com>
[Squash Robert's and Ian's commits for bisectability, update patch
 description and add stable tag]
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts
index 78bfc1a307d60c61ad340d979959748e7abdd564..ebc6e10f86240d70b1f2c4851d6920f929831613 100644 (file)
--- a/arch/arm/boot/dts/imx6q-b450v3.dts
+++ b/arch/arm/boot/dts/imx6q-b450v3.dts
@@ -65,13 +65,6 @@
        };
 };
 
-&clks {
-       assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
-                         <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
-       assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
-                                <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
-};
-
 &ldb {
        status = "okay";
 

diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts
index d853887254268aae304f3a90b244bef3cdc07990..681aa612e07f793dfc2520322124692579dc327a 100644 (file)
--- a/arch/arm/boot/dts/imx6q-b650v3.dts
+++ b/arch/arm/boot/dts/imx6q-b650v3.dts
@@ -65,13 +65,6 @@
        };
 };
 
-&clks {
-       assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
-                         <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
-       assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
-                                <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
-};
-
 &ldb {
        status = "okay";
 

diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts
index e5e9a16155d979c6b0861a30776ba771b3587763..8596df4078e9e8eb807100a67725dfcd9fb78f9a 100644 (file)
--- a/arch/arm/boot/dts/imx6q-b850v3.dts
+++ b/arch/arm/boot/dts/imx6q-b850v3.dts
@@ -53,17 +53,6 @@
        };
 };
 
-&clks {
-       assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
-                         <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
-                         <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
-                         <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
-       assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
-                                <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
-                                <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
-                                <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
-};
-
 &ldb {
        fsl,dual-channel;
        status = "okay";

diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
index ff8928a0b40650f1865af066b530191a79759b7a..cee0e19f180fbaaef71e2c58c30a5a297f821942 100644 (file)
--- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi
+++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
@@ -361,3 +361,18 @@
                #interrupt-cells = <1>;
        };
 };
+
+&clks {
+       assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+                         <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+                         <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
+                         <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>,
+                         <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>,
+                         <&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>;
+       assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+                                <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
+};