arm64: dts: mediatek: mt7622: add support for coherent DMA

[ Upstream commit 3abd063019b6a01762f9fccc39505f29d029360a ]

It improves performance by eliminating the need for a cache flush on rx and tx

Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: David S. Miller <davem@davemloft.net>
Stable-dep-of: 3ba5a6159434 ("arm64: dts: mediatek: mt7622: fix clock controllers")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index a4c48b2abd209979e1d51a5538459c022933e2f6..8a332a3d3718a0c88cfcec014f19b05111c5e6c1 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -357,7 +357,7 @@ cci_control1: slave-if@4000 {
                };
 
                cci_control2: slave-if@5000 {
-                       compatible = "arm,cci-400-ctrl-if";
+                       compatible = "arm,cci-400-ctrl-if", "syscon";
                        interface-type = "ace";
                        reg = <0x5000 0x1000>;
                };
@@ -938,6 +938,8 @@ eth: ethernet@1b100000 {
                power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
                mediatek,ethsys = <&ethsys>;
                mediatek,sgmiisys = <&sgmiisys>;
+               mediatek,cci-control = <&cci_control2>;
+               dma-coherent;
                #address-cells = <1>;
                #size-cells = <0>;
                status = "disabled";