PCI/ACPI: Add Ampere Altra SOC MCFG quirk

commit 877c1a5f79c6984bbe3f2924234c08e2f4f1acd5 upstream.

Ampere Altra SOC supports only 32-bit ECAM reads.  Add an MCFG quirk for
the platform.

Link: https://lore.kernel.org/r/1596751055-12316-1-git-send-email-tuanphan@os.amperecomputing.com
Signed-off-by: Tuan Phan <tuanphan@os.amperecomputing.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
[ dannf: backport drops const qualifier from pci_32b_read_ops for
  consistency with the other quirks that weren't yet constified in v5.4 ]
Signed-off-by: dann frazier <dann.frazier@canonical.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index 6b347d9920cc217843ebf1dd21eac1c9514762be..47e43c949825746351f49da8ccddead2e00a5ab8 100644 (file)
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -142,6 +142,26 @@ static struct mcfg_fixup mcfg_quirks[] = {
        XGENE_V2_ECAM_MCFG(4, 0),
        XGENE_V2_ECAM_MCFG(4, 1),
        XGENE_V2_ECAM_MCFG(4, 2),
+
+#define ALTRA_ECAM_QUIRK(rev, seg) \
+       { "Ampere", "Altra   ", rev, seg, MCFG_BUS_ANY, &pci_32b_read_ops }
+
+       ALTRA_ECAM_QUIRK(1, 0),
+       ALTRA_ECAM_QUIRK(1, 1),
+       ALTRA_ECAM_QUIRK(1, 2),
+       ALTRA_ECAM_QUIRK(1, 3),
+       ALTRA_ECAM_QUIRK(1, 4),
+       ALTRA_ECAM_QUIRK(1, 5),
+       ALTRA_ECAM_QUIRK(1, 6),
+       ALTRA_ECAM_QUIRK(1, 7),
+       ALTRA_ECAM_QUIRK(1, 8),
+       ALTRA_ECAM_QUIRK(1, 9),
+       ALTRA_ECAM_QUIRK(1, 10),
+       ALTRA_ECAM_QUIRK(1, 11),
+       ALTRA_ECAM_QUIRK(1, 12),
+       ALTRA_ECAM_QUIRK(1, 13),
+       ALTRA_ECAM_QUIRK(1, 14),
+       ALTRA_ECAM_QUIRK(1, 15),
 };
 
 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];

diff --git a/drivers/pci/ecam.c b/drivers/pci/ecam.c
index 1a81af0ba961a96d23c9c99310f4288dd9114200..9765d2eb79d212dc858932cacd463a980f09fa7c 100644 (file)
--- a/drivers/pci/ecam.c
+++ b/drivers/pci/ecam.c
@@ -164,4 +164,14 @@ struct pci_ecam_ops pci_32b_ops = {
                .write          = pci_generic_config_write32,
        }
 };
+
+/* ECAM ops for 32-bit read only (non-compliant) */
+struct pci_ecam_ops pci_32b_read_ops = {
+       .bus_shift      = 20,
+       .pci_ops        = {
+               .map_bus        = pci_ecam_map_bus,
+               .read           = pci_generic_config_read32,
+               .write          = pci_generic_config_write,
+       }
+};
 #endif

diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
index a73164c85e78b904bcbce317897c531a5130a6df..75456a66024a934932959aecb19d6fb848c4904d 100644 (file)
--- a/include/linux/pci-ecam.h
+++ b/include/linux/pci-ecam.h
@@ -51,6 +51,7 @@ extern struct pci_ecam_ops pci_generic_ecam_ops;
 
 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
 extern struct pci_ecam_ops pci_32b_ops;                /* 32-bit accesses only */
+extern struct pci_ecam_ops pci_32b_read_ops; /* 32-bit read only */
 extern struct pci_ecam_ops hisi_pcie_ops;      /* HiSilicon */
 extern struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 1.x & 2.x */
 extern struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */