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arm64: dts: qcom: sm8450: Fix missing iommus for qup
author
Vinod Koul
<vkoul@kernel.org>
Thu, 14 Apr 2022 10:16:25 +0000
(15:46 +0530)
committer
Greg Kroah-Hartman
<gregkh@linuxfoundation.org>
Thu, 9 Jun 2022 08:30:24 +0000
(10:30 +0200)
[ Upstream commit
488922c1a372579bf2caf40933e7459e3c86276f
]
qupv3_id_0 was missing iommus property which cause any dma transaction
to fail and board crash. So add the missing iommus.
While at it also add interconnect nodes for qup
Fixes: 5188049c9b36 ("arm64: dts: qcom: Add base SM8450 DTSI")
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link:
https://lore.kernel.org/r/20220414101630.1189052-3-vkoul@kernel.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/arm64/boot/dts/qcom/sm8450.dtsi
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diff --git
a/arch/arm64/boot/dts/qcom/sm8450.dtsi
b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 934e29b9e153b5c73b33115a6e4aee8019c8b2bb..5facb4a5bf6354e3b9340c839531759aaac4cdc0 100644
(file)
--- a/
arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/
arch/arm64/boot/dts/qcom/sm8450.dtsi
@@
-693,6
+693,9
@@
qupv3_id_0: geniqup@9c0000 {
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x5a3 0x0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
+ interconnect-names = "qup-core";
#address-cells = <2>;
#size-cells = <2>;
ranges;