ARM: dts: imx6qdl-apalis: Fix sgtl5000 detection issue

[ Upstream commit fa51e1dc4b91375bc18349663a52395ad585bd3c ]

On a custom carrier board with a i.MX6Q Apalis SoM, the sgtl5000 codec
on the SoM is often not detected and the following error message is
seen when the sgtl5000 driver tries to read the ID register:

sgtl5000 1-000a: Error reading chip id -6

The reason for the error is that the MCLK clock is not provided
early enough.

Fix the problem by describing the MCLK pinctrl inside the codec
node instead of placing it inside the audmux pinctrl group.

With this change applied the sgtl5000 is always detected on every boot.

Fixes: 693e3ffaae5a ("ARM: dts: imx6: Add support for Toradex Apalis iMX6Q/D SoM")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index 05f07ea3e8c8051338dfec9db3977e095ae19431..ed783c91b002a855abcff0aff0b0b4412f3dac19 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -313,6 +313,8 @@
        codec: sgtl5000@a {
                compatible = "fsl,sgtl5000";
                reg = <0x0a>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_sgtl5000>;
                clocks = <&clks IMX6QDL_CLK_CKO>;
                VDDA-supply = <&reg_module_3v3_audio>;
                VDDIO-supply = <&reg_module_3v3>;
@@ -540,8 +542,6 @@
                        MX6QDL_PAD_DISP0_DAT21__AUD4_TXD        0x130b0
                        MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS       0x130b0
                        MX6QDL_PAD_DISP0_DAT23__AUD4_RXD        0x130b0
-                       /* SGTL5000 sys_mclk */
-                       MX6QDL_PAD_GPIO_5__CCM_CLKO1            0x130b0
                >;
        };
 
@@ -807,6 +807,12 @@
                >;
        };
 
+       pinctrl_sgtl5000: sgtl5000grp {
+               fsl,pins = <
+                       MX6QDL_PAD_GPIO_5__CCM_CLKO1    0x130b0
+               >;
+       };
+
        pinctrl_spdif: spdifgrp {
                fsl,pins = <
                        MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0