drm/i915/gvt: Fix kernel oops for 3-level ppgtt guest

[ Upstream commit 72a7a9925e2beea09b109dffb3384c9bf920d9da ]

As i915 won't allocate extra PDP for current default PML4 table,
so for 3-level ppgtt guest, we would hit kernel pointer access
failure on extra PDP pointers. So this trys to bypass that now.
It won't impact real shadow PPGTT setup, so guest context still
works.

This is verified on 4.15 guest kernel with i915.enable_ppgtt=1
to force on old aliasing ppgtt behavior.

Fixes: 4f15665ccbba ("drm/i915: Add ppgtt to GVT GEM context")
Reviewed-by: Xiong Zhang <xiong.y.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20200506095918.124913-1-zhenyuw@linux.intel.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 685d1e04a5ff6ee9b82cd11cd6c74b8a215c9270..709ad181bc94a59faf64369ac98116a8f2813dbd 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -375,7 +375,11 @@ static void set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload,
                for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) {
                        struct i915_page_directory * const pd =
                                i915_pd_entry(ppgtt->pd, i);
-
+                       /* skip now as current i915 ppgtt alloc won't allocate
+                          top level pdp for non 4-level table, won't impact
+                          shadow ppgtt. */
+                       if (!pd)
+                               break;
                        px_dma(pd) = mm->ppgtt_mm.shadow_pdps[i];
                }
        }