drm/radeon/dpm: Disable sclk switching on Oland when two 4K 60Hz monitors are connected
authorKai-Heng Feng <kai.heng.feng@canonical.com>
Fri, 30 Apr 2021 04:56:56 +0000 (12:56 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sat, 22 May 2021 08:59:45 +0000 (10:59 +0200)
commit 227545b9a08c68778ddd89428f99c351fc9315ac upstream.

Screen flickers rapidly when two 4K 60Hz monitors are in use. This issue
doesn't happen when one monitor is 4K 60Hz (pixelclock 594MHz) and
another one is 4K 30Hz (pixelclock 297MHz).

The issue is gone after setting "power_dpm_force_performance_level" to
"high". Following the indication, we found that the issue occurs when
sclk is too low.

So resolve the issue by disabling sclk switching when there are two
monitors requires high pixelclock (> 297MHz).

v2:
 - Only apply the fix to Oland.
Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_pm.c
drivers/gpu/drm/radeon/si_dpm.c

index 1a6f6edb3515188ea55e3ce8e2b9d2e951d0c8c7..62e6e3b73e4e6a5b8ed63e91d0b68e7626c6649a 100644 (file)
@@ -1558,6 +1558,7 @@ struct radeon_dpm {
        void                    *priv;
        u32                     new_active_crtcs;
        int                     new_active_crtc_count;
+       int                     high_pixelclock_count;
        u32                     current_active_crtcs;
        int                     current_active_crtc_count;
        bool single_display;
index 4b6542538ff91581272deadb6e971c50f2429033..c213a5c9227edbe9c7bc47303c36704e82587c80 100644 (file)
@@ -1715,6 +1715,7 @@ static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
        struct drm_device *ddev = rdev->ddev;
        struct drm_crtc *crtc;
        struct radeon_crtc *radeon_crtc;
+       struct radeon_connector *radeon_connector;
 
        if (!rdev->pm.dpm_enabled)
                return;
@@ -1724,6 +1725,7 @@ static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
        /* update active crtc counts */
        rdev->pm.dpm.new_active_crtcs = 0;
        rdev->pm.dpm.new_active_crtc_count = 0;
+       rdev->pm.dpm.high_pixelclock_count = 0;
        if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
                list_for_each_entry(crtc,
                                    &ddev->mode_config.crtc_list, head) {
@@ -1731,6 +1733,12 @@ static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
                        if (crtc->enabled) {
                                rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
                                rdev->pm.dpm.new_active_crtc_count++;
+                               if (!radeon_crtc->connector)
+                                       continue;
+
+                               radeon_connector = to_radeon_connector(radeon_crtc->connector);
+                               if (radeon_connector->pixelclock_for_modeset > 297000)
+                                       rdev->pm.dpm.high_pixelclock_count++;
                        }
                }
        }
index db2d8b84e137be8182b32cf6c0df1a78498eeec6..aac18d527c01ba3e020742fe41fb7d44ad78c219 100644 (file)
@@ -3000,6 +3000,9 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
                    (rdev->pdev->device == 0x6605)) {
                        max_sclk = 75000;
                }
+
+               if (rdev->pm.dpm.high_pixelclock_count > 1)
+                       disable_sclk_switching = true;
        }
 
        if (rps->vce_active) {