parisc: Mark cr16 clock unstable on all SMP machines

commit 340233dcc0160aafcce46ca893d1679f16acf409 upstream.

The cr16 interval timers are not synchronized across CPUs, even with just
one dual-core CPU. This becomes visible if the machines have a longer
uptime.

Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/parisc/kernel/time.c b/arch/parisc/kernel/time.c
index 08e4d480abe184620cb54c09965c3ddb35d02ed1..d8e59a1000ab7c4333b2b791ef15986eb3fd455e 100644 (file)
--- a/arch/parisc/kernel/time.c
+++ b/arch/parisc/kernel/time.c
@@ -249,33 +249,14 @@ void __init time_init(void)
 static int __init init_cr16_clocksource(void)
 {
        /*
-        * The cr16 interval timers are not syncronized across CPUs on
-        * different sockets, so mark them unstable and lower rating on
-        * multi-socket SMP systems.
+        * The cr16 interval timers are not synchronized across CPUs.
         */
        if (num_online_cpus() > 1 && !running_on_qemu) {
-               int cpu;
-               unsigned long cpu0_loc;
-               cpu0_loc = per_cpu(cpu_data, 0).cpu_loc;
-
-               for_each_online_cpu(cpu) {
-                       if (cpu == 0)
-                               continue;
-                       if ((cpu0_loc != 0) &&
-                           (cpu0_loc == per_cpu(cpu_data, cpu).cpu_loc))
-                               continue;
-
-                       clocksource_cr16.name = "cr16_unstable";
-                       clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE;
-                       clocksource_cr16.rating = 0;
-                       break;
-               }
+               clocksource_cr16.name = "cr16_unstable";
+               clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE;
+               clocksource_cr16.rating = 0;
        }
 
-       /* XXX: We may want to mark sched_clock stable here if cr16 clocks are
-        *      in sync:
-        *      (clocksource_cr16.flags == CLOCK_SOURCE_IS_CONTINUOUS) */
-
        /* register at clocksource framework */
        clocksource_register_hz(&clocksource_cr16,
                100 * PAGE0->mem_10msec);