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x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN
authorTony Luck <tony.luck@intel.com>
Fri, 19 Mar 2021 17:39:19 +0000 (10:39 -0700)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sat, 5 Feb 2022 11:37:55 +0000 (12:37 +0100)
commit a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab upstream.

New CPU model, same MSRs to control and read the inventory number.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20210319173919.291428-1-tony.luck@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/x86/kernel/cpu/mce/intel.c patch | blob | history

diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index 2577d787578102c5175ee6c8c4776dc957abf2bf..7cf08c1f082e0a37cbc028ff7e27aa2abf0b37c2 100644 (file)
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
        case INTEL_FAM6_BROADWELL_X:
        case INTEL_FAM6_SKYLAKE_X:
        case INTEL_FAM6_ICELAKE_X:
+       case INTEL_FAM6_SAPPHIRERAPIDS_X:
        case INTEL_FAM6_XEON_PHI_KNL:
        case INTEL_FAM6_XEON_PHI_KNM:
 
wrapfs-3.14.y