From: David Abdurachmanov Date: Sun, 13 Jun 2021 00:43:57 +0000 (-0700) Subject: riscv: dts: fu740: fix cache-controller interrupts X-Git-Tag: v5.12.14~50 X-Git-Url: https://git.fsl.cs.sunysb.edu/?a=commitdiff_plain;h=8bfb7c12758ab95035758b7722a51c900f71f30e;p=wrapfs-4.14.y.git riscv: dts: fu740: fix cache-controller interrupts [ Upstream commit 7ede12b01b59dc67bef2e2035297dd2da5bfe427 ] The order of interrupt numbers is incorrect. The order for FU740 is: DirError, DataError, DataFail, DirFail From SiFive FU740-C000 Manual: 19 - L2 Cache DirError 20 - L2 Cache DirFail 21 - L2 Cache DataError 22 - L2 Cache DataFail Signed-off-by: David Abdurachmanov Signed-off-by: Palmer Dabbelt Signed-off-by: Sasha Levin --- diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index eeb4f8c3e0e7..d0d206cdb999 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -272,7 +272,7 @@ cache-size = <2097152>; cache-unified; interrupt-parent = <&plic0>; - interrupts = <19 20 21 22>; + interrupts = <19 21 22 20>; reg = <0x0 0x2010000 0x0 0x1000>; }; gpio: gpio@10060000 {